(1) Field of the Invention
This invention relates to a solid-state image pickup device for use in a television camera etc. Particularly it relates to a solid-state imaging device which has a plurality of picture elements and horizontal and vertical scanning circuits, both of which are disposed in surface regions of a semiconductor body. More specifically, it relates to a solid-state device which has picture elements for reading out from photodiodes optical information stored therein.
(2) Description of the Prior Art
A solid-state imaging device functions to convert optical information into time-sequential electric signals. In order to achieve a high resolution, it comprises approximately 500.times.500 photoelectric conversion elements, switching transistors for X-Y addressing corresponding to the elements, and an X-scanner (horizontal scanning circuit) and a Y-scanner (vertical scanning circuit) which deliver scan pulses for turning the switching transistors "on" and "off." A principle construction becomes as shown in FIG. 1. Hereunder the prior art will be described with reference to the drawings, in which the same symbols designate the same or equivalent parts. In FIG. 1, numeral 1 designates a horizontal scanner, which consists of unit circuits in the number of stages corresponding to the number of photoelectric conversion elements arrayed in the horizontal direction (for example, 500). On the basis of clock pulses for driving the scanner 1, scan pulses which shift every predetermined timing interval are sequentially provided from the respective unit circuits in a horizontal scan period. Numeral 101 indicates a horizontal scan line which transmits the horizontal scan pulse. Numeral 2 designates a vertical scanner, which consists of unit circuits in the number of stages corresponding to the number of rows of the photoelectric conversion elements (for example, 500). On the basis of clock pulses for driving the scanner 2, scan pulses which shift every fixed timing interval are sequentially provided from the respective unit circuits in correspondence with the horizontal scan period during one field. Numeral 102 indicates a vertical scan line which transmits the vertical scan pulse. With the two trains of scan pulses, vertical switching transistors 3 and horizontal switching transistors 6 are sequentially turned "on" and "off" so that signals from the individual photoelectric conversion elements 4 arrayed in two dimensions may be taken out onto vertical output lines 5 and a horizontal output line 7. Since the signal from each photoelectric conversion element 4 corresponds to the optical image of an object projected thereon, a video signal can be derived by the above operation.
The solid-state imaging device is ordinarily fabricated by the use of the MOS-LSI technology which can realize a high packed integration comparatively easily and according to which the photoelectric conversion element and the switching transistor can be produced by an integral structure as has a structural section shown in FIG. 2. As seen from the figure, the vertical switching transistor is made up of a MOS (metal-oxide-semiconductor) field effect transistor (hereinbelow, abbreviated to "MOST") 3 which is provided with a gate 8 on which the vertical scan pulse is impressed. The photoelectric conversion element 4 is formed of a pn (or np-) junction photodiode which exploits the source junction of the MOST 3. The vertical output line 5 is formed of an interconnection (usually, made of A1) which is spliced with the drain of the MOST 3. The horizontal switching transistor is made up of a MOST 6 which is provided with a gate 9 on which the horizontal scan pulse is impressed. The horizontal output line 7 is formed of an interconnection (usually, made of A1) which is spliced with the drain of the MOST 6. Numeral 10 represents a semiconductor (e.g., silicon) body in which these elements are integrated. The semiconductor body 10 has the n-type conductivity (or p-type conductivity) when the sources and drains are impurity layers of the p-type conductivity (or the n-type conductivity). Numeral 11 indicates an insulating film (in general, silicon dioxide (SiO.sub.2) film). The solid-state imaging device thus constructed has such excellent merits that the source junction of the MOST can be exploited as the photoelectric conversion element, and that a MOS shift register can be utilized for the scanning circuit and be integrally formed on the semiconductor body.
The solid-state imaging device of this type, however, involves problems to be stated below in relation to the construction thereof.
1. Scanning circuitry
In case of an areal solid-state imaging device, the scanning circuitry consists of the horizontal scanner for performing the scanning in the X direction and the vertical scanner for performing the scanning in the Y direction. The horizontal scanner needs to scan all the photoelectric conversion elements arranged in the X direction in the scan pulse output period of the vertical scanner (64 .mu.s in the standard television format, 15.73 kHz in terms of the frequency). Accordingly, the scanning rate required for the horizontal scanner becomes the number of picture elements in the X direction-times (by way of example, 500 times in a device including 500 (X direction) .times.500 (Y direction) picture elements) as high as the scanning rate of the vertical scanner. In many cases, however, the horizontal and vertical scanners are circuits of the same arrangement and are made by an identical process of fabrication.
The unit circuit of each stage of a typical scanner having heretofore been employed (refer to Material SSD72-36 of the Society for the Research of Semiconductors and Transistors, Denshi Tsushin Gakkai--the Institute of Electronics and Communication) is a shift register type circuit which is constructed of one set of inverter circuits and one set of transfer gates as shown in FIG. 3A. The figure illustrates the first stage being a constituent unit of the shift register type scanner, and also a driver circuit portion therefor. Numerals 12 and 13 designate generators which generate clock pulses with their phases shifting by 180.degree.. Numeral 14 indicates an input pulse generator which generates an input pulse V.sub.IN for obtaining a shift pulse at an output terminal 16 of a unit circuit 15. Shown at 17 is a driving power supply. Numeral 18 represents a transfer MOST which is turned "on" and "off" by the clock pulse .phi..sub.1, while numeral 19 denotes a transfer MOST which is turned "on" and "off" by the clock pulse .phi..sub.2. Shown at 20 is an inverter circuit, which is made up of a series connection consisting of a saturation type load MOST 21 with its gate and drain being spliced to the identical power supply 17 and a driver MOST 22.
FIG. 3B is a timing chart of the input and output pulses obtained with the present circuit. Upon impression of the input pulse V.sub.IN synchronous with the clock pulse .phi..sub.2, the output pulse V.sub.01 which has the same polarity as that of the input pulse V.sub.IN and which is delayed by the period T.sub..phi. of the clock pulses is provided from the output terminal 16. The output pulse V.sub.01 also becomes an input to the next stage (not shown), and an output pulse V.sub.02 which is similarly delayed by the period T.sub..phi. is provided from an output terminal of the next stage. Subsequently, a train of output pulses V.sub.03 . . . which are delayed every T.sub..phi. in the same manner can be provided. Regarding the output pulses, the rising time t.sub.r ("0".fwdarw."1") is a period of time in which a capacitance C.sub.s parasitic to the output terminal 16 is charged by the load MOST. On the other hand, the falling time t.sub.f ("1".fwdarw."0") is a period of time which is required in order that the "1" voltage stored in the stray capacity C.sub.s may be discharged through the driver MOST 22. In order to effect the inverting operation, the conductance of the load MOST 21 is ordinarily selected at about 1/10 of the conductance of the drive MOST 22. For this reason, the rising time is one order greater than the falling time, and it is the rising time or the conductance of the load MOST 21 which determines the upper limit of the operating speed to be attained by the present scanner. It is accordingly necessary that the conductance g.sub.ml.sup.H of the load MOST which constitutes the horizontal scanner operating at a high speed is selected to be greater than the conductance g.sub.ml.sup.V of the load MOST which constitutes the vertical scanner operating at a low speed.
In this respect, however, it is desirable to manufacture both the scanners by the identical process of fabrication. Without any contrivance, the conductances of the MOST's constituting both the scanners will naturally become equal. Accordingly, the design value (e.g., the channel width or the channel length) of the MOST constituting the horizontal scanner needs to be made different so as to enhance the conductance. However, to bestow a difference of two or more orders merely by changing the design value is unfavorable in incurring such a drawback that the layout area occupied by the horizontal scanner becomes extremely large.
2. Switches
The horizontal switching transistor 6 is addressed every 64 .mu.s in the standard television format by the high-speed horizontal scanner 1, and the vertical output line is charged up to a video voltage every 64 .mu.s, whereas the vertical switching transistor 3 is addressed every approximately 17 ms (the field frequency is 60 Hz). Thus, the photodiode 4 operates in the so-called storage mode in which the diode is irradiated by light for 17 ms and stores therein optical signal charges generated during the time, so that the photosensitivity becomes high. The turn-off resistance of the MOST is high as compared with those of other elements such as bipolar transistor. However, even when a voltage applied to the gate is below the threshold voltage of the MOST, the transistor is not perfectly cut off but a minute current (usually called the "tailing current") flows therethrough, so that the photodiode 4 is charged through the vertical switching MOST 3. It is therefore impossible to read out a signal which reflects the optical information accurately.
3. Noise
Inductive noise which are attributed to the rise and fall of the clock pulse for driving the horizontal scanner 1 or the scan pulse delivered from each stage of the scanner leak to the horizontal signal output line 7 through stray capacitances inside or outside the semiconductor body. (Noise which are generated by the clock pulse for driving the vertical scanner or the scan pulse from the scanner pose no problem because the noise can be, in effect, eliminated from the video signal in such a way that the clock pulses are covered within a horizontal blanking period provided every horizontal scan period.) In particular, noise which arrive through the interior of the semiconductor body mix via complicated paths under the action of the resistance of the semiconductor body besides the stray capacitances. It is therefore very difficult to remove the noise by a noise processing circuit (for which a low-pass filter is generally used). For this reason, as compared with a pickup tube, the solid-state imaging device has a low signal-to-noise ratio and exhibits a poor picture quality, so that the device has the fields of application limited or its practical use hindered.